Physical Unclonable Function (PUF)

Fully integrated
Margin-check mechanism
Robust architecture
Low power consumption
Silicon proven

Stable 256-bit key generated from random local process variations
Reliable bits selected through a margin check mechanism
Reliable bits stable over voltage, temperature and aging
Typical operating lifetime higher than 10 years
Gate count of the digital controller smaller than 25 kgates
Typical characteristics of a 55 nm CMOS implementation:

• operating junction temperature range: -40°C to 125°C
• generation of the first 256-bit key in less than 210 µs at 50 MHz
• generation of the following 256-bit keys in less than 20 µs at 50 MHz
• typical operating current of the analog core during bit reading smaller than 20 µA
• typical standby current of the analog core smaller than 10 nA
• silicon area of the analog core smaller than 0.02 mm²

Silicon proven in 65 nm and 55 nm CMOS processes

GDSII stream and layer map file
Library Exchange Format (LEF) file
Circuit Description Language (CDL) netlist
Liberty Timing File (.lib)
VHDL behavioral model
Design specification