Secure Clock Generator

The Secure Clock Generator is a fully integrated mixed-signal IP securing the clocked system against side-channel attacks.



​Fully integrated
Programmable range
Accurate​ frequency
On-the-fly modulation
Optional jitter


Fully integrated secure clock generator
Programmable frequency range (customized on request)
Frequency accuracy better than ±10% through trimming process
Frequency monitor protecting against fault injection attacks
Jittered clock option protecting against side-channel attacks
Secondary clock signal generated by on-the-fly period masking
Robust power-up, power-down and standby sequences avoiding clock glitches
Operating junction temperature range: -40°C to 125°C
Characteristics of a 55 nm CMOS implementation:

  • power supply voltage range: 1.2 V ±10%
  • typical wake-up time shorter than 20 µs
  • typical operating current consumption lower than 120 µA at 120 MHz
  • silicon area smaller than 0.045 mm²

Proven track record through mass production in 130 nm and 55 nm CMOS processe
Silicon proven in 130 nm, 65 nm and 55 nm CMOS processes


GDSII stream and layer map file
Library Exchange Format (LEF) file
Circuit Description Language (CDL) netlist
Liberty Timing File (.lib)
VHDL behavioral model
Design specification