True Random Number Generator - Digital Noise Source

​Robust architecture
Standard-cell based
Thermal noise extraction
Low footprint
FPGA proven

​Robust, low-footprint, standard-cell based entropy source
Entropy generation through thermal noise extraction
Compliant with the statistical tests of the AIS31 and FIPS SP 800-90 standards
Random stream synchronization via external sampling clock
Generic implementation compatible with most FPGAs
FPGA proven on the Intel Arria 10 FPGA SoC line
Typical size on a Intel Arria 10 SX 660: 100 ALM
Digital post-processing available separately

​Encrypted netlist
Design specification