LVDS Transceiver

​​​The LVDS Transceiver is a fully integrated Low-Voltage Differential Signaling analog front end including one flow-through driver and two flow-through receivers



Fully integrated
High bit rates
Straightforward synchronization
Small area
Silicon proven


Fully-integrated Low Voltage Differential Signaling (LDVS) transceiver
Two flow-through LVDS receivers
One flow-through LVDS driver
Upstream and downstream bit rates up to 500 Mbit/s
Straightforward output stream synchronization through an external sampling clock
Power-supply voltage range:

  • core side: nominal core supply voltage ±10%
  • I/O side: nominal I/O supply voltage ±10%

Characteristics of a 90 nm CMOS implementation:

  • core side supply voltage: 1.2 V ±10%
  • I/O side supply voltage: 1.8 V ±10%
  • operating current: 4 mA per receiver and 8 mA per driver (500 Mbit/s; Cload=10 pF)
  • standby supply current lower than 250 µA
  • silicon area smaller than 0.32 mm²

Silicon proven in a 90 nm CMOS process


GDSII stream and layer map file
Library Exchange Format (LEF) file
Circuit Description Language (CDL) netlist
Liberty Timing File (.lib)
VHDL behavioral model
Design specification