LASER Pulse Detector

​​The LASER Pulse Detector is a fully integrated mixed-signal IP detecting bit-flipping attacks.



High sensitivity
Standard cell like
Ultra low power
Very compact
Easy integration


Analog-based architecture packaged as a standard cell
Straightforward integration within the digital logic area
Full-custom layout optimized for an hyper sensitivity to laser pulses
Detection threshold lower than bit-flipping energy levels​
Form factor equivalent to that of 2.5 NAND2 gates
Typical characteristics of a 55 nm CMOS implementation:

  • power supply voltage range: 1.2 V ±10%
  • operating junction temperature range: -40°C to 125°C
  • ​typical operating current smaller than 100 pA​
  • Y dimension: 1.4 µm (height of a standard cell)
  • X dimension: 1.8 µm (length of 2.5 NAND2 gates)

​Silicon proven in a 55 nm CMOS process
Successfully evaluated by a security laboratory​


GDSII stream and layer map file
Library Exchange Format (LEF) file
Circuit Description Language (CDL) netlist
Liberty Timing File (.lib and .db)
VHDL behavioral model
Design specification