EPC Gen2 Digital Controller

EPC Gen2 compliant
Silicon proven
Small gate count​
Optimized implementation​​
Straightforward integration

Fully compliant with the EPC Gen2 standard
RX frame decoding, command execution and TX frame coding
Custom commands on request
Total gate count smaller than 10 kgates
Operating power consumption lower than 10 µW
Straightforward interfacing with the memory block
Silicon proven in a 110 nm CMOS process
Analog front end available separately

VHDL source code
VHDL testbenches
Synopsys synthesis scripts
Design specification